1. Field of the Invention
The present invention relates to a lightly-doped drain (LDD) fabrication, and more particularly, to a method of forming LDD by automatic phosphoric silicate glass (PSG) doping.
2. Description of the Prior Art
In the semiconductor process, there is a problem about "hot electron effect" induced by short channel MOS transistor. The problem is solved by implanting impurities to form the lightly-doped regions. The implantation impurity concentration of the lightly-doped regions is lower than the original source/drain regions. The lightly-doped regions mainly prevent hot electron effect and serve as the LDD (lightly-doped drain).
In a conventional LDD fabrication, there are-typically two methods used as follow:
The first method is used by an ion implantation to form the LDD. Referring to FIG. 1A, an isolation process such as a standard LOCOS (Local Oxidation of Silicon) is performed. Then, field oxide layers (FOX) 102 are formed on a substrate 100 to define an active area 104. A gate oxide layer 106 and a polysilicon layer 108 are sequentially formed over the substrate 100 and on the field oxide layers (FOX) 102. A photoresist 110 is patterned on the polysilicon layer 108, covering a portion of the top surface of the polysilicon layer 108 to define a gate electrode region.
Referring to FIG. 1B, an etching process is performed by using the photoresist 110 as an etching mask. The unmasked portion of the polysilicon layer 108 is etched to the surface of the gate oxide layer 106. After the etching process, a gate electrode 112 is formed. Next, the photoresist 110 is removed. The gate oxide layer 106 can reduce ions to collide with the silicon atoms in the substrate during the subsequent ion implantation process. The ions will not be deeply driven into the substrate to form "channeling effect".
Afterwards, referring to FIG. 1C, the gate oxide layer 106 and the field oxide layers 102 are utilized as the shielding mask for implanting impurities into the substrate. Next, a thermal annealing. process is performed to form lightly-doped regions 114.
Afterwards, referring to FIG. 1D, a dielectric layer 116 is formed on the gate electrode 112 and the gate oxide layer 106.
Next, referring to FIG. 1E, an anisotropic etching process, such as a reactive ion etch, is performed to etch the dielectric layer 116, forming sidewall spacers 118 on the sidewalls of the gate electrode 112. The sidewall spacers 118 and the gate electrode 112 are utilized as the shielding mask for implanting impurities to form the heavily-doped regions, thereby forming the source/drain regions 120.
Accordingly, the conventional ion implantation method will usually cause the damage of the substrate 100, and increase the leakage current. Additionally, the lightly-doped regions (LDD) 114 are formed by using the thermal annealing process to diffuse impurities into the substrate 100. Therefore, the conventional method can not effectively control the diffusing depth of impurities and the concentration distribution of impurities.
Another method uses a phosphoric silicate glass (PSG) as a diffusion source. The ions of phosphoric silicate glass (PSG) are driven into the substrate by a thermal treatment process to form the lightly-doped regions (LDD). Referring FIG. 2A, after an isolation process such as a standard LOCOS (Local Oxidation of Silicon) is performed, field oxide layers (FOX) 202 are formed on a substrate 200 to define an active area 204. A gate oxide layer 206 and a polysilicon layer 208 are sequentially formed over the substrate 200 and on the field oxide layers (FOX) 202. A photoresist 210 is patterned on the polysilicon layer 208, covering a portion of the top surface of the polysilicon layer 208 to define a gate electrode region.
Referring to FIG. 2B, an etching process is performed by using the photoresist 210 as an etching mask. The unmasked portions of the gate oxide layer 206 and the polysilicon layer 208 are etched to the surface of the substrate 200. After the etching process, a gate electrode 212 is formed. Next, the photoresist 210 is removed.
Referring to FIG. 2C, a phosphoric silicate glass (PSG) 214 is formed on the gate electrode 212 and the substrate 200 by a chemical vapor deposition process. Thereafter, a thermal annealing process is performed. The phosphorous (P) ions of the phosphoric silicate glass (PSG) 214 are driven into the substrate 200 to form the lightly-doped regions (LDD) 216.
Referring to FIG. 2D, an anisotropic etching process, such as a reactive ion etch, is performed. Then, sidewall spacers 218 are formed on the sidewalls of the gate electrode 212 by etching the phosphoric silicate glass (PSG) 214. The sidewall spacers 218 and the gate electrode 212 are utilized as the shielding mask for implanting impurities to form the heavily-doped regions, thereby forming the source/drain regions 220.
Accordingly, the method uses the phosphoric silicate glass (PSG) 214 as a diffusion source to form the lightly-doped drain (LDD) 216. The ions of phosphoric silicate glass (PSG) 214 will still sequentially be driven into the substrate 200 during the subsequent thermal treatment process, for example, the annealing process or the flow process of dielectric planarization. Therefore, the impurity concentration of the lightly-doped regions 216 will increase. Additionally, the conventional method also can not effectively control the diffusing depth of impurities and the concentration distribution of impurities. Therefore, the subsequent compensation of implanting impurities to form a preferred lightly-doped regions will be very difficult to perform.